How are the control signals derived in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction will propagate through the pipeline with no effect. There is no data path defined for a jump that tells the processor to change the PC. The only thing that changes the PC (aside from the normal PC+4) is a beq.

I'm learning about MIPS pipelining and stages, but what is excruciatingly unclear is how a jump instruction is executed. On an assignment question, I'm asked to trace the pipeline with the command "j 16", but there does not appear to be any details about how the logic is handled. The closest thing I can find of any relevance is to do with beq, but the opcodes are different... beq is 000100 and j is 000010. The following table outlines how the control codes work for four classes of opcodes, but it doesn't explain what happens for jump, and subsequently, how the machine knows to jump and what it does with the command...

So, if I have the instruction 000010 00000000000000000000000100, how does this get handled by the data path?

You are correct. The above data path doesn't have the parts that support jump instruction. Yet, those are easy to add.

The pipelined datapath in your question is based on a single-cycle MIPS that doesn't support jumps (Figure 5.21 in Patterson and Hennessy). In order to add jump support, consider the single-cycle MIPS datapath of Figure 5.24; then add the jump parts to the pipelined architecture.

However, note that jumps and branches must be treated correctly in order to avoid control hazards - specifically, new instructions that entered the pipe after the jump should not be executed. The complete datapath that takes care of control hazards (again, for branches only) appears in Figure 6.41.

StackExchange Computer Science Q#20093, answer score: 2