Why we need to read memory on a write-miss?

I noticed that in write-back caches, when the cpu wants to write to a block, it fetches the block from memory and then updates it. If the block is going to be overwritten and changed by processor, why does the cpu need to read that block from memory?

While it would be possible to construct a 128-bit wide memory bus with a separate write-enable control for each octet (sixteen in all), doing so would generally be more expensive than designing the bus to require that any operation which writes to any byte in a 128-bit cache line must supply data for all sixteen. Although there are times when being able to update some bytes in a line without having to read the others would yield a performance advantage, in many cases the penalty of having to fill a cache line from memory sometime between when the fist write gets posted and when the line gets flushed will be minimal, and the benefits of eliminating that penalty may be insufficient to justify the cost of the extra write-control logic.

StackExchange Computer Science Q#21318, answer score: 3