Does the aliasing problem show up in a virtually indexed physically tagged cache?

Basically, and as a simple method, we can access cache with Physical Address which is from the TLB.

But, as another method, we can access cache with Virtual Address. But, in this case, if the cache is not fully flushed between context switch(other process's datas can be exist in cache), there is an aliasing problem. Same memory can be directed from the different virtual address.

But in my text book, including these problem, many can be solved by virtually indexed physically tagged. I think this still can make an aliasing problem.

Am I wrong?

The Aliasing problem can be solved if we select the cache size small enough. If cache size is such that the bits for indexing the cache all come from the page offset bits , multiple virtual address will point to the same index position in the cache and aliasing will be solved.

For example consider 32-bit virtual address 0xFFFF FFFF , this system uses a page size of 64kB suppose which make the page offset bits 16 bits. Now if we select The index bits to be 10 (number of sets 1024) and block size as 64 Bytes. Then the index bits and the block offset bits both are accommodated in the page offset bits of the virtual address. Consider another address 0xEEEE FFFF this address looks like it will cause aliasing but despite of having different virtual address the lower order bits force it to map to the same location in the cache and there is no aliasing. Only drawback of this approach is cache size is limited by the page size.

StackExchange Computer Science Q#68492, answer score: 7