Why is a 4 KB alignment requirement imposed on Intel Core i7 page tables for Linux

I'm reading CSAPP and couldn't wrap my head around this part:

Summary of what the section says:

• Intel Core i7 support a 48-bit virtual address space and 52-bit physical address space.

• Core i7 uses a four-level page table hierarchy.

Then the book shows a picture of the breakdown of a PTE:

Please note the 40-bit PPN.

It goes on to say that "the 40-bit PPN points to the beginning of the appropriate page table. Notice that this imposes a 4 KB alignment requirement on page tables".

My question is what does the bolded line mean? And why there is a 4 KB alignment requirement? I know (theoretically) how virtual memory and page tables work but don't get this alignment requirement.

To further explain my confusion: What does it mean to say "...alignment requirement on page tables"? Does it mean that the PTE has to be 4KB in chunk (this was described a page before and doesn't really seem to need any further proof), or something else?

The physical address for the start of a page frame or page table is obtained by taking the 40-bit PPN and appending 12 zero bits. That gives you a 52-bit physical address, which is the start of the frame or page table.

A consequence is that frames or page tables must start at a physical address that is a multiple of $2^{12}=4096$, i.e., that is aligned at a multiple of 4KB.

StackExchange Computer Science Q#147771, answer score: 23