snippetbashTip

verilator — Convert Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC m

Submitted by: @import:tldr-pages·Mar 2, 2026·

Viewed 0 times

commandverilatorhardwaresystemverilogandconvertcliverilog

Problem

How to use the verilator command: Convert Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling. More information: <https://veripool.org/guide/latest/>.

Solution

verilator — Convert Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling. More information: <https://veripool.org/guide/latest/>.

Build a specific C project in the current directory:

verilator --binary --build-jobs 0 -Wall {{path/to/source.v}}

Create a C++ executable in a specific folder:

verilator --cc --exe --build --build-jobs 0 -Wall {{path/to/source.cpp}} {{path/to/output.v}}

Perform linting over a code in the current directory:

verilator --lint-only -Wall

Create XML output about the design (files, modules, instance hierarchy, logic, and data types) to feed into other tools:

verilator --xml-output -Wall {{path/to/output.xml}}

Code Snippets

Build a specific C project in the current directory

verilator --binary --build-jobs 0 -Wall {{path/to/source.v}}

Create a C++ executable in a specific folder

verilator --cc --exe --build --build-jobs 0 -Wall {{path/to/source.cpp}} {{path/to/output.v}}

Perform linting over a code in the current directory

verilator --lint-only -Wall

Create XML output about the design (files, modules, instance hierarchy, logic, and data types) to feed into other tools

verilator --xml-output -Wall {{path/to/output.xml}}

Context

tldr-pages: common/verilator

Revisions (0)

No revisions yet.