ALU design for a 16-bit microprocessor

I'm having a hard time figuring out if the code I wrote is purely combinatorial or sequential logic. I'm designing a simple 16-bit microprocessor (will be implemented on a Spartan 6), and I'm new to Verilog, HDL and FPGAs. The code for the microprocessor is complete, but I'm having second thoughts about the best practices behind the code.

I'm aware that since this is the first time coding for me, the code is not up to any standard, but I tried my best.

One of the most important elements is the ALU, and it has been designed like any other person would. It has overflow/underflow detection which I also asked about here, and I quickly wrote some code for it, which may or may not be correct.

But, my question is whether I should be using the non-blocking operator (<=) or blocking operator (=) in the always block for the ALU. I know the standard practice is to use the blocking operator while designing combinatorial circuits versus using the non-blocking one, which is better for sequential circuits.

If I was to use blocking operators in the always block for the ALU, would the synthesized version be slower than if I use non-blocking operators? I plan to use the on-board 100MHz clock on my development board, so I was wondering if the ALU could keep up.

Here's the full code for the ALU:

```
module alu(clk, rst, en, re, opcode, a_in, b_in, o, z, n, cond, d_out);

// Parameter Definitions

parameter width = 'd16; // ALU Width

// Inputs

input wire clk / System Clock Input /, rst / Reset Result Register /, en / Enables ALU Processing /, re / ALU Read Enable /;
input wire [4:0] opcode / 5-bit Operation Code for the ALU. Refer to documentation. /;
input wire signed [width-1:0] a_in / Operand A Input Port /, b_in / Operand B Input Port /;

// Outputs

output wire z / Zero Flag Register (Embedded in res_out) /, n / Negative/Sign Flag Register /;
output reg o / Overflow/Underflow/Carry Flag Register /;
output reg cond / Conditional Flag Register /;
out

non-blocking one, which is better for sequential circuits.

It is not better per-se but it is the correct way to simulate a flip-flop.

Combinatorial

always @* begin
  a = b;

Sequential (flip-flop)

always @(posedge clock) begin
  a <= b ;

In the examples above nothing would go wrong if you used the wrong type but think about

always @(posedge clock) begin
  b <= c ;
  a <= b ;

Which is the same as

always @(posedge clock) begin
  a <= b ;
  b <= c ;

We are specifying a delay line which is c -> b -> a. If we use the wrong type :

always @(posedge clock) begin
  b = c ;
  a = b ; //=c

We actually get c -> b and c -> a, b does not block and feeds directly into a. Mixing the styles is possible but unless done very carefully bugs can creep in. for the purpose of code review it is best not to mix them so that it is a clear cut case.

Which will give a different result to :

always @(posedge clock) begin
  a = b ;
  b = c ;

When implying parallel hardware you would not expect an order dependence like this.

Mixing styles, or using the wrong style can lead to RTL vs Gate level mismatch. ie using a <= in a combinatorial section always @* will give the desired result in simulation but synthesis will ignore this and give you the equivalent of =.

StackExchange Code Review Q#56322, answer score: 7