Clock mux for allowing glitch-free muxing of asynchronous clocks

This clock mux is meant to allow glitch-free muxing between asynchronous clocks clk_a and clk_b via a (also asynchronous to both clocks) sel signal.

I'm looking for any feedback, but in particular I'm looking for confirmation that there can be no output glitches or metastability issues assuming synchronous/related paths meet timing and that one period of either clock is long enough for a 2-flop synchronizer to allow potential metastable states to settle.

Additionally, I'm interested in ways to improve the switchover time or reduce the FF/LUT utilization.

```
library ieee;
use ieee.std_logic_1164.all;

entity clk_mux is
port(
clk_a : in std_logic;
clk_b : in std_logic;
clk_o : out std_logic;
sel : in std_logic
);
end clk_mux;

architecture rtl of clk_mux is
--combinational
signal clk_i : std_logic;

--async set for disabled clock's lock to ensure internal select can safely be turned low again on first rising edge of the new active clock
signal lock_a : std_logic; --despite being combinational, output always last's exactly 1/2 the period of the other clock and cannot have glitches (inputs never change near each other in time)
signal lock_b : std_logic;

--FF
--ensures the disabled clock can't be re-enabled until the currently enabled clock is disabled
signal force_a_lock : std_logic := '0';
signal force_b_lock : std_logic := '1';

--forces the respective clock being disabled high (and keeps it that way) its rising edge to prevent output glitches
signal force_a_re : std_logic := '0';
signal force_b_re : std_logic := '1';

--releases the forcing on the falling edge (also to prevent output glitches)
signal force_a_fe : std_logic := '0';
signal force_b_fe : std_logic := '1';

--sel is syncronized and pulse extended to 2 cycles of active clock to prevent internal select from changing right as final rising of edge of the old active clock happens
signal sel_sync : std_l

I found a good paper some weeks ago for this topic, but currently I can't find the online source. While searching I found another paper1 on the net.

The presented solution should be glitch free, but the circuit is not hardened for meta stability problems. You can improve this by using double flip-flops.

Here is a schematic of the circuit in the paper that I could not find anymore.

1 B. Jovanović and M. Damnjanović, "Glitch Free Clock Switching Techniques in Modern Microcontrollers," in Proceedings of the 5th Small Systems Simulation Symposium, 2014, pp. 119–122.

StackExchange Code Review Q#62097, answer score: 5