16-bit Parity Generator

I have completed a VHDL 16-bit parity generator and I would like to know if I have programmed it correctly. I have compiled it 10 times and worked out any bugs that it found. I was finally able to compile it successfully. My problem is that I am trying to run a timing simulation to make sure it will work correctly but I am not sure what I should be looking for.

The basic operation is to XOR the A and B inputs to perform an iterative process with an output of '1' as odd and an output of '0' as even. My code is written such that a basic XOR block is then added as a component of the complete parity generator.

I would like a second opinion to make sure I have written it correctly and if it will do what it is designed to do. I thank you all in advance and look forward to any input, good or bad.

Basic XOR gate block VHDL Code

library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
port(
        a : in std_logic;
        b : in std_logic;
        pari : in std_logic;
        paro : out std_logic);

    end xor_gate;

architecture behavior of xor_gate is
    begin

    paro <= (a xor b) or pari;

end behavior;

16-bit Parity Generator Code

library ieee;
use ieee.std_logic_1164.all;
entity parity_2 is

port(a: in std_logic_vector (0 to 15);
      b: in std_logic_vector (0 to 15);
      paro: out std_logic);

end parity_2;

architecture behavior of parity_2 is
        signal parry: std_logic_vector (0 to 15);

component xor_gate
            port (a,b: in std_logic;
                   pari: in std_logic;
                    paro: out std_logic);

end component;

begin

c1: xor_gate port map (a(0), b(0), '0', parry(0));
c: for i in 1 to 15 generate
c2: xor_gate port map (parry(i-1), a(i), b(i), parry(i));

end generate;

paro <= parry(15);

end behavior;

As mentioned in the comments the or part of your "xor_gate" prevents it from actually working as an xor gate to calculate bit parity.

Instead your paro signal will be '0' when a=b and '1' when a/=b (the 16 bit vectors, not the bits within xor_gate). If that was your intended functionality, then paro <= '0' when a=b else '1'; would be simpler.

Finally, it would be much clearer and cleaner to not have a whole component for such a simple operation. The following does an xor of all the bits (a typical parity calculation) and is shorter and easier to read. If I was only going to use this calculation in one or two places, I'd absorb this whole block into those as well, as it is only 6 additional lines.

library ieee;
use ieee.std_logic_1164.all;
entity parity_2 is
  port(a: in std_logic_vector (0 to 15);
       b: in std_logic_vector (0 to 15);
       paro: out std_logic
      );
end parity_2;

architecture behavior of parity_2 is
  signal parry: std_logic_vector (0 to 15);
begin

parry(0) <= a(0) xor b(0);
c: for i in 1 to 15 generate
  parry(i) <= parry(i-1) xor a(i) xor b(i); 
end generate;

paro <= parry(15);

end behavior;

StackExchange Code Review Q#87986, answer score: 3